\ This program is distributed under the terms of the 'MIT license'. The text \ of this licence follows... \ \ Copyright (c) 2005 J.D.Medhurst (a.k.a. Tixy) \ \ Permission is hereby granted, free of charge, to any person obtaining a copy \ of this software and associated documentation files (the "Software"), to deal \ in the Software without restriction, including without limitation the rights \ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell \ copies of the Software, and to permit persons to whom the Software is \ furnished to do so, subject to the following conditions: \ \ The above copyright notice and this permission notice shall be included in \ all copies or substantial portions of the Software. \ \ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR \ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, \ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE \ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER \ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, \ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN \ THE SOFTWARE. \ \ \ ---------------------------------------------------------------------------- \ CHANGES \ \ 2006-11-09 \ Fixed some ANS Forth Standard compliancey issues. \ * Made all hex values use upper-case letters. HEX \ ---------------------------------------------------------------------------- \ Tests which generate random (or sequential) op-codes and check that \ assembler and disassembler are consistant with each other... ALSO ARM-DISASSEMBLER ALSO ARM-ASSEMBLER ALSO PRIVATE-WORDLIST ALSO FORTH VARIABLE RANDOM-SEED 1 RANDOM-SEED ! : RANDOM ( -- x ) RANDOM-SEED @ 10DCD * 1+ DUP RANDOM-SEED ! ; : H. ( u -- ) \ Display u in hex BASE @ >R HEX 0 <# # # # # # # # # #> R> BASE ! TYPE SPACE ; : CLEANUP-OP ( x1 -- x2 ) \ Make op-code unambiguous DUP 0E000000 AND 02000000 = IF \ make data literal match format used by assembler DUP FFFFF000 AND SWAP DUP 0FF AND SWAP F00 AND 7 RSHIFT RROTATE ARM-DATA-LITERAL OR THEN DUP 0E000FFF AND 04000000 = IF 01800000 OR \ Force 0 index to be pre up index THEN DUP 0E0000FF AND 0C000000 = IF 01800000 OR \ Force 0 index to be pre up index THEN DUP 0E400F9F AND 00400090 = IF 01800000 OR \ Force 0 index to be pre up index THEN DUP FFF801C0 AND F1080000 = IF 000001C0 OR \ Force iflags in CPSIE/ID to be not zero THEN DUP 0DB00000 AND 01200000 = IF 000F0000 OR \ Force field_mask in MSR to be not zero THEN DUP 0F8000F0 AND 06800070 = IF FFFFFCFF AND \ Force SBZ fields in extend instructions THEN ; \ : BREAKPOINT ." BREAKPOINT" QUIT ; : TEST ( -- ) \ Test assembler and disassembler are consistant with each other CODE-HERE 3 + 3 INVERT AND CODE-HERE! ALSO ARM-ASSEMBLER 1 \ true for random instructions, false for all instructions in sequence DUP IF -10000 \ Test 10000 (hex) random instructions ELSE D0000000 \ Test all instruction D0000000-FFFFFFFF THEN >R BEGIN DUP IF RANDOM ELSE R@ DUP FFF AND 0= IF DUP H. CR THEN THEN CLEANUP-OP >R CODE-HERE R@ DEPTH >R ARM-DISASM-OP DEPTH R> <> IF ." DISASM STACK DEPTH MISMATCH " R@ H. .S BREAKPOINT THEN \ R@ FF AND 0= IF 2DUP TYPE CR THEN \ 2DUP TYPE CR \ KEY DROP 2DUP S" UNDEFINED" EQUAL 0= IF DEPTH >R CODE-HERE >R 0 CODE-HERE ! CODE-HERE CODE-ORIGIN ! OP-RESET 2DUP ['] EVALUATE CATCH ?DUP IF ." EXCEPTION " . KEY DROP THEN OP-END CODE-HERE 1 CELLS - R@ <> IF ." CODE-HERE MISMATCH" R@ H. CODE-HERE H. CR TYPE BREAKPOINT THEN R> CODE-HERE! DEPTH R> <> IF ." ASM STACK DEPTH MISMATCH " R@ H. .S BREAKPOINT THEN R@ CODE-HERE @ <> IF \ assembler didn't produce same op-code as was disassembled... UNPREDICTABLE @ IF R@ CODE-HERE @ XOR \ bits which differ UNPREDICTABLE @ INVERT AND IF ." UNPREDICTABLE FAIL " UNPREDICTABLE @ H. R@ H. CODE-HERE H. BREAKPOINT THEN \ 2DUP TYPE CR ELSE ." FAIL " CODE-HERE H. R@ H. CODE-HERE @ H. 2DUP TYPE CR BREAKPOINT THEN THEN THEN 2DROP R> DROP R> 1+ DUP >R 0= UNTIL R> DROP PREVIOUS ; \ ---------------------------------------------------------------------------- \ Words to test specific test cases... : QUOTE ( c-addr u -- c-addr u ) \ display string in double quotes [CHAR] " EMIT 2DUP TYPE [CHAR] " EMIT SPACE ; : >" ( x "ccc" -- ) BASE @ >R HEX >R [CHAR] " PARSE R@ H. QUOTE CR 0 R@ DEPTH >R ARM-DISASM-OP DEPTH R> <> IF CR ." DISASM STACK DEPTH FAIL " .S KEY DROP THEN 9 SPACES QUOTE 2OVER EQUAL 0= IF CR ." DISASM FAIL" KEY DROP THEN DEPTH >R ALSO ARM-ASSEMBLER 0 CODE-ORIGIN ! OP-RESET ['] EVALUATE CATCH ?DUP IF ." EXCEPTION " . KEY DROP THEN OP-VALUE @ PREVIOUS R> DEPTH <> IF CR ." ASM STACK DEPTH FAIL " .S KEY DROP THEN DUP H. CR R> <> IF CR ." ASM FAIL" KEY DROP THEN R> BASE ! ; PREVIOUS PREVIOUS PREVIOUS PREVIOUS \ ---------------------------------------------------------------------------- \ Test cases... .( TEST CASES ) CR CR 00A21003 >" adc eq r1 r2 r3" 10A21003 >" adc ne r1 r2 r3" 20A21003 >" adc cs r1 r2 r3" \ also hs 30A21003 >" adc cc r1 r2 r3" \ also lo 40A21003 >" adc mi r1 r2 r3" 50A21003 >" adc pl r1 r2 r3" 60A21003 >" adc vs r1 r2 r3" 70A21003 >" adc vc r1 r2 r3" 80A21003 >" adc hi r1 r2 r3" 90A21003 >" adc ls r1 r2 r3" A0A21003 >" adc ge r1 r2 r3" B0A21003 >" adc lt r1 r2 r3" C0A21003 >" adc gt r1 r2 r3" D0A21003 >" adc le r1 r2 r3" E0A21003 >" adc r1 r2 r3" \ also al C0A21003 >" adc gt r1 r2 r3" C0B21003 >" adc gt s r1 r2 r3" C0A21203 >" adc gt r1 r2 r3 lsl 4 #" C0A21413 >" adc gt r1 r2 r3 lsl r4" C0A21023 >" adc gt r1 r2 r3 lsr 20 #" C0A21223 >" adc gt r1 r2 r3 lsr 4 #" C0A21433 >" adc gt r1 r2 r3 lsr r4" C0A21043 >" adc gt r1 r2 r3 asr 20 #" C0A21243 >" adc gt r1 r2 r3 asr 4 #" C0A21453 >" adc gt r1 r2 r3 asr r4" C0A21263 >" adc gt r1 r2 r3 ror 4 #" C0A21FE3 >" adc gt r1 r2 r3 ror 1F #" C0A21473 >" adc gt r1 r2 r3 ror r4" C0A21063 >" adc gt r1 r2 r3 rrx" C2A21034 >" adc gt r1 r2 34 #" C2B21034 >" adc gt s r1 r2 34 #" C2ACB034 >" adc gt r11 r12 34 #" C2A21FFF >" adc gt r1 r2 3FC #" C2A211FF >" adc gt r1 r2 -3FFFFFC1 #" C0821003 >" add gt r1 r2 r3" C0021003 >" and gt r1 r2 r3" CA000000 >" b gt 8 #" CAFFFFFC >" b gt FFFFFFF8 #" CB000000 >" bl gt 8 #" CBFFFFFC >" bl gt FFFFFFF8 #" C1C21003 >" bic gt r1 r2 r3" E1212374 >" bkpt 1234 #" \ ARM 5 E12FED7C >" bkpt 0FEDC #" FA000000 >" blx 8 #" \ ARM 5 FAFFFFFC >" blx FFFFFFF8 #" FB000000 >" blx 0A #" FBFFFFFC >" blx FFFFFFFA #" C12FFF31 >" blx gt r1" \ ARM 5 C12FFF3B >" blx gt r11" C12FFF11 >" bx gt r1" \ ARM 4T + 5 C12FFF1B >" bx gt r11" C12FFF21 >" bxj gt r1" \ ARM 5J + 6 C12FFF2B >" bxj gt r11" CE2431C5 >" cdp gt p1 2 # c3 c4 c5 6 #" CE534622 >" cdp gt p6 5 # c4 c3 c2 1 #" FE2431C5 >" cdp2 p1 2 # c3 c4 c5 6 #" \ ARM 5 C16F1F12 >" clz gt r1 r2" \ ARM 5 C16FBF1C >" clz gt r11 r12" C1710002 >" cmn gt r1 r2" C17B000C >" cmn gt r11 r12" C1510002 >" cmp gt r1 r2" C15B000C >" cmp gt r11 r12" C0221003 >" eor gt r1 r2 r3" CD932100 >" ldc gt p1 c2 [ r3 ]" CD93C100 >" ldc gt p1 c12 [ r3 ]" CD9D2100 >" ldc gt p1 c2 [ r13 ]" CD932B00 >" ldc gt p11 c2 [ r3 ]" CC932104 >" ldc gt p1 c2 [ r3 ] { 4 # }" CC9321FF >" ldc gt p1 c2 [ r3 ] { 0FF # }" CCD32104 >" ldc gt l p1 c2 [ r3 ] { 4 # }" CC332104 >" ldc gt p1 c2 [ r3 ] -10 #" CCB32104 >" ldc gt p1 c2 [ r3 ] 10 #" CC732104 >" ldc gt l p1 c2 [ r3 ] -10 #" CCF32104 >" ldc gt l p1 c2 [ r3 ] 10 #" CD132104 >" ldc gt p1 c2 [ r3 -10 # ]" CD932104 >" ldc gt p1 c2 [ r3 10 # ]" CD532104 >" ldc gt l p1 c2 [ r3 -10 # ]" CDD32104 >" ldc gt l p1 c2 [ r3 10 # ]" CD332104 >" ldc gt p1 c2 [ r3 -10 # ] !" CDB32104 >" ldc gt p1 c2 [ r3 10 # ] !" CD732104 >" ldc gt l p1 c2 [ r3 -10 # ] !" CDF32104 >" ldc gt l p1 c2 [ r3 10 # ] !" FD932100 >" ldc2 p1 c2 [ r3 ]" C8110004 >" ldm gt da r1 { r2 }" C9110004 >" ldm gt db r1 { r2 }" C8910004 >" ldm gt ia r1 { r2 }" C9910004 >" ldm gt ib r1 { r2 }" C811800C >" ldm gt da r1 { r2 r3 pc }" C81E800C >" ldm gt da lr { r2 r3 pc }" C8110000 >" ldm gt da r1 { }" \ unpredictable C8310004 >" ldm gt da r1 ! { r2 }" C831800C >" ldm gt da r1 ! { r2 r3 pc }" C8510004 >" ldm gt da r1 { r2 } ^" C9510004 >" ldm gt db r1 { r2 } ^" C8D10004 >" ldm gt ia r1 { r2 } ^" C9D10004 >" ldm gt ib r1 { r2 } ^" C871000C >" ldm gt da r1 ! { r2 r3 } ^" \ unpredictable C871800C >" ldm gt da r1 ! { r2 r3 pc } ^" C5921000 >" ldr gt r1 [ r2 ]" C59CB000 >" ldr gt r11 [ r12 ]" C5921004 >" ldr gt r1 [ r2 4 # ]" C5921FFF >" ldr gt r1 [ r2 0FFF # ]" C5121004 >" ldr gt r1 [ r2 -4 # ]" C7921003 >" ldr gt r1 [ r2 r3 ]" C792100D >" ldr gt r1 [ r2 r13 ]" C7121003 >" ldr gt r1 [ r2 -r3 ]" C7921083 >" ldr gt r1 [ r2 r3 lsl 1 # ]" C7921F83 >" ldr gt r1 [ r2 r3 lsl 1F # ]" C79210A3 >" ldr gt r1 [ r2 r3 lsr 1 # ]" C7921023 >" ldr gt r1 [ r2 r3 lsr 20 # ]" C79210C3 >" ldr gt r1 [ r2 r3 asr 1 # ]" C79210E3 >" ldr gt r1 [ r2 r3 ror 1 # ]" C7921063 >" ldr gt r1 [ r2 r3 rrx ]" C7121083 >" ldr gt r1 [ r2 -r3 lsl 1 # ]" C5B21004 >" ldr gt r1 [ r2 4 # ] !" C5B21FFF >" ldr gt r1 [ r2 0FFF # ] !" C5321004 >" ldr gt r1 [ r2 -4 # ] !" C7B21003 >" ldr gt r1 [ r2 r3 ] !" C7B2100D >" ldr gt r1 [ r2 r13 ] !" C7321003 >" ldr gt r1 [ r2 -r3 ] !" C7B21083 >" ldr gt r1 [ r2 r3 lsl 1 # ] !" C7B210A3 >" ldr gt r1 [ r2 r3 lsr 1 # ] !" C7B210C3 >" ldr gt r1 [ r2 r3 asr 1 # ] !" C7B210E3 >" ldr gt r1 [ r2 r3 ror 1 # ] !" C7B21063 >" ldr gt r1 [ r2 r3 rrx ] !" C7321083 >" ldr gt r1 [ r2 -r3 lsl 1 # ] !" C4921004 >" ldr gt r1 [ r2 ] 4 #" C4921FFF >" ldr gt r1 [ r2 ] 0FFF #" C4121004 >" ldr gt r1 [ r2 ] -4 #" C6921003 >" ldr gt r1 [ r2 ] r3" C692100D >" ldr gt r1 [ r2 ] r13" C6121003 >" ldr gt r1 [ r2 ] -r3" C6921083 >" ldr gt r1 [ r2 ] r3 lsl 1 #" C69210A3 >" ldr gt r1 [ r2 ] r3 lsr 1 #" C69210C3 >" ldr gt r1 [ r2 ] r3 asr 1 #" C69210E3 >" ldr gt r1 [ r2 ] r3 ror 1 #" C6921063 >" ldr gt r1 [ r2 ] r3 rrx" C6121083 >" ldr gt r1 [ r2 ] -r3 lsl 1 #" C4B21000 >" ldr gt t r1 [ r2 ]" C4B21004 >" ldr gt t r1 [ r2 ] 4 #" C6B21003 >" ldr gt t r1 [ r2 ] r3" C6B21083 >" ldr gt t r1 [ r2 ] r3 lsl 1 #" C4321004 >" ldr gt t r1 [ r2 ] -4 #" C6321003 >" ldr gt t r1 [ r2 ] -r3" C6321083 >" ldr gt t r1 [ r2 ] -r3 lsl 1 #" C5D21000 >" ldr gt b r1 [ r2 ]" C5D21004 >" ldr gt b r1 [ r2 4 # ]" C7D21083 >" ldr gt b r1 [ r2 r3 lsl 1 # ]" C5F21004 >" ldr gt b r1 [ r2 4 # ] !" C7F21003 >" ldr gt b r1 [ r2 r3 ] !" C7F21003 >" ldr gt b r1 [ r2 r3 ] !" C4D21004 >" ldr gt b r1 [ r2 ] 4 #" C6D21003 >" ldr gt b r1 [ r2 ] r3" C6D21083 >" ldr gt b r1 [ r2 ] r3 lsl 1 #" C5521004 >" ldr gt b r1 [ r2 -4 # ]" C7521083 >" ldr gt b r1 [ r2 -r3 lsl 1 # ]" C5721004 >" ldr gt b r1 [ r2 -4 # ] !" C7721003 >" ldr gt b r1 [ r2 -r3 ] !" C7721003 >" ldr gt b r1 [ r2 -r3 ] !" C4521004 >" ldr gt b r1 [ r2 ] -4 #" C6521003 >" ldr gt b r1 [ r2 ] -r3" C6521083 >" ldr gt b r1 [ r2 ] -r3 lsl 1 #" C4F21000 >" ldr gt bt r1 [ r2 ]" C4F21004 >" ldr gt bt r1 [ r2 ] 4 #" C6F21003 >" ldr gt bt r1 [ r2 ] r3" C6F21083 >" ldr gt bt r1 [ r2 ] r3 lsl 1 #" C4721004 >" ldr gt bt r1 [ r2 ] -4 #" C6721003 >" ldr gt bt r1 [ r2 ] -r3" C6721083 >" ldr gt bt r1 [ r2 ] -r3 lsl 1 #" C1D210B0 >" ldr gt h r1 [ r2 ]" \ ARM4 C1D210BF >" ldr gt h r1 [ r2 0F # ]" C1D21FB0 >" ldr gt h r1 [ r2 0F0 # ]" C15210BF >" ldr gt h r1 [ r2 -F # ]" C1521FB0 >" ldr gt h r1 [ r2 -F0 # ]" C19210B3 >" ldr gt h r1 [ r2 r3 ]" C19210BD >" ldr gt h r1 [ r2 r13 ]" C11210B3 >" ldr gt h r1 [ r2 -r3 ]" C1F210BF >" ldr gt h r1 [ r2 0F # ] !" C17210BF >" ldr gt h r1 [ r2 -F # ] !" C1B210B3 >" ldr gt h r1 [ r2 r3 ] !" C13210B3 >" ldr gt h r1 [ r2 -r3 ] !" C0D210BF >" ldr gt h r1 [ r2 ] 0F #" C05210BF >" ldr gt h r1 [ r2 ] -F #" C09210B3 >" ldr gt h r1 [ r2 ] r3" C01210B3 >" ldr gt h r1 [ r2 ] -r3" C1D210F0 >" ldr gt sh r1 [ r2 ]" \ ARM4 C1D210FF >" ldr gt sh r1 [ r2 0F # ]" C1D21FF0 >" ldr gt sh r1 [ r2 0F0 # ]" C15210FF >" ldr gt sh r1 [ r2 -F # ]" C1521FF0 >" ldr gt sh r1 [ r2 -F0 # ]" C19210F3 >" ldr gt sh r1 [ r2 r3 ]" C19210FD >" ldr gt sh r1 [ r2 r13 ]" C11210F3 >" ldr gt sh r1 [ r2 -r3 ]" C1F210FF >" ldr gt sh r1 [ r2 0F # ] !" C17210FF >" ldr gt sh r1 [ r2 -F # ] !" C1B210F3 >" ldr gt sh r1 [ r2 r3 ] !" C13210F3 >" ldr gt sh r1 [ r2 -r3 ] !" C0D210FF >" ldr gt sh r1 [ r2 ] 0F #" C05210FF >" ldr gt sh r1 [ r2 ] -F #" C09210F3 >" ldr gt sh r1 [ r2 ] r3" C01210F3 >" ldr gt sh r1 [ r2 ] -r3" C1D210D0 >" ldr gt sb r1 [ r2 ]" \ ARM4 C1D210DF >" ldr gt sb r1 [ r2 0F # ]" C1D21FD0 >" ldr gt sb r1 [ r2 0F0 # ]" C15210DF >" ldr gt sb r1 [ r2 -F # ]" C1521FD0 >" ldr gt sb r1 [ r2 -F0 # ]" C19210D3 >" ldr gt sb r1 [ r2 r3 ]" C19210DD >" ldr gt sb r1 [ r2 r13 ]" C11210D3 >" ldr gt sb r1 [ r2 -r3 ]" C1F210DF >" ldr gt sb r1 [ r2 0F # ] !" C17210DF >" ldr gt sb r1 [ r2 -F # ] !" C1B210D3 >" ldr gt sb r1 [ r2 r3 ] !" C13210D3 >" ldr gt sb r1 [ r2 -r3 ] !" C0D210DF >" ldr gt sb r1 [ r2 ] 0F #" C05210DF >" ldr gt sb r1 [ r2 ] -F #" C09210D3 >" ldr gt sb r1 [ r2 ] r3" C01210D3 >" ldr gt sb r1 [ r2 ] -r3" CE4431D5 >" mcr gt p1 2 # r3 c4 c5 6 #" CEA34632 >" mcr gt p6 5 # r4 c3 c2 1 #" CEA34612 >" mcr gt p6 5 # r4 c3 c2 0 #" FEA34612 >" mcr2 p6 5 # r4 c3 c2 0 #" C0214392 >" mla gt r1 r2 r3 r4" C0241293 >" mla gt r4 r3 r2 r1" C0314392 >" mla gt s r1 r2 r3 r4" C3A01002 >" mov gt r1 2 #" C1A01002 >" mov gt r1 r2" C1A0B00C >" mov gt r11 r12" C1A01182 >" mov gt r1 r2 lsl 3 #" C1A01312 >" mov gt r1 r2 lsl r3" C1B01002 >" mov gt s r1 r2" CE5431D5 >" mrc gt p1 2 # r3 c4 c5 6 #" CEB34632 >" mrc gt p6 5 # r4 c3 c2 1 #" CEB34612 >" mrc gt p6 5 # r4 c3 c2 0 #" FEB34612 >" mrc2 p6 5 # r4 c3 c2 0 #" C10F1000 >" mrs gt r1 cpsr" C10FB000 >" mrs gt r11 cpsr" C14F1000 >" mrs gt r1 spsr" C121F001 >" msr gt cpsr_ c r1" C122F001 >" msr gt cpsr_ x r1" C123F001 >" msr gt cpsr_ cx r1" C124F001 >" msr gt cpsr_ s r1" C125F001 >" msr gt cpsr_ cs r1" C126F001 >" msr gt cpsr_ xs r1" C127F001 >" msr gt cpsr_ cxs r1" C128F001 >" msr gt cpsr_ f r1" C129F001 >" msr gt cpsr_ cf r1" C12AF001 >" msr gt cpsr_ xf r1" C12BF001 >" msr gt cpsr_ cxf r1" C12CF001 >" msr gt cpsr_ sf r1" C12DF001 >" msr gt cpsr_ csf r1" C12EF001 >" msr gt cpsr_ xsf r1" C12FF001 >" msr gt cpsr_ cxsf r1" C321F001 >" msr gt cpsr_ c 1 #" C321F0FF >" msr gt cpsr_ c 0FF #" C161F001 >" msr gt spsr_ c r1" C361F0FF >" msr gt spsr_ c 0FF #" C0010392 >" mul gt r1 r2 r3" C0040293 >" mul gt r4 r3 r2" C0110392 >" mul gt s r1 r2 r3" C3E01002 >" mvn gt r1 2 #" C1E01002 >" mvn gt r1 r2" C1E0B00C >" mvn gt r11 r12" C1E01182 >" mvn gt r1 r2 lsl 3 #" C1E01312 >" mvn gt r1 r2 lsl r3" C1F01002 >" mvn gt s r1 r2" C1821003 >" orr gt r1 r2 r3" C0621003 >" rsb gt r1 r2 r3" C0E21003 >" rsc gt r1 r2 r3" C0C21003 >" sbc gt r1 r2 r3" CD832100 >" stc gt p1 c2 [ r3 ]" CD83C100 >" stc gt p1 c12 [ r3 ]" CD8D2100 >" stc gt p1 c2 [ r13 ]" CD832B00 >" stc gt p11 c2 [ r3 ]" CC832104 >" stc gt p1 c2 [ r3 ] { 4 # }" CC8321FF >" stc gt p1 c2 [ r3 ] { 0FF # }" CCC32104 >" stc gt l p1 c2 [ r3 ] { 4 # }" CC232104 >" stc gt p1 c2 [ r3 ] -10 #" CCA32104 >" stc gt p1 c2 [ r3 ] 10 #" CC632104 >" stc gt l p1 c2 [ r3 ] -10 #" CCE32104 >" stc gt l p1 c2 [ r3 ] 10 #" CD032104 >" stc gt p1 c2 [ r3 -10 # ]" CD832104 >" stc gt p1 c2 [ r3 10 # ]" CD432104 >" stc gt l p1 c2 [ r3 -10 # ]" CDC32104 >" stc gt l p1 c2 [ r3 10 # ]" CD232104 >" stc gt p1 c2 [ r3 -10 # ] !" CDA32104 >" stc gt p1 c2 [ r3 10 # ] !" CD632104 >" stc gt l p1 c2 [ r3 -10 # ] !" CDE32104 >" stc gt l p1 c2 [ r3 10 # ] !" FD832100 >" stc2 p1 c2 [ r3 ]" C0E21493 >" smlal gt r1 r2 r3 r4" C0F21493 >" smlal gt s r1 r2 r3 r4" C0C21493 >" smull gt r1 r2 r3 r4" C0D21493 >" smull gt s r1 r2 r3 r4" C8010004 >" stm gt da r1 { r2 }" C9010004 >" stm gt db r1 { r2 }" C8810004 >" stm gt ia r1 { r2 }" C9810004 >" stm gt ib r1 { r2 }" C801800C >" stm gt da r1 { r2 r3 pc }" C80E800C >" stm gt da lr { r2 r3 pc }" C8010000 >" stm gt da r1 { }" \ unpredictable C8210004 >" stm gt da r1 ! { r2 }" C821800C >" stm gt da r1 ! { r2 r3 pc }" C8410004 >" stm gt da r1 { r2 } ^" C9410004 >" stm gt db r1 { r2 } ^" C8C10004 >" stm gt ia r1 { r2 } ^" C9C10004 >" stm gt ib r1 { r2 } ^" C861000C >" stm gt da r1 ! { r2 r3 } ^" \ unpredictable C861800C >" stm gt da r1 ! { r2 r3 pc } ^" \ unpredictable C5821000 >" str gt r1 [ r2 ]" C4A21000 >" str gt t r1 [ r2 ]" C5C21000 >" str gt b r1 [ r2 ]" C5421004 >" str gt b r1 [ r2 -4 # ]" C4E21000 >" str gt bt r1 [ r2 ]" C1C210B0 >" str gt h r1 [ r2 ]" \ ARM4 C0421003 >" sub gt r1 r2 r3" CF123456 >" swi gt 123456 #" C1031092 >" swp gt r1 r2 [ r3 ]" C10DB09C >" swp gt r11 r12 [ r13 ]" C1431092 >" swp gt b r1 r2 [ r3 ]" C14DB09C >" swp gt b r11 r12 [ r13 ]" C13B000C >" teq gt r11 r12" C11B000C >" tst gt r11 r12" C0A21493 >" umlal gt r1 r2 r3 r4" C0B21493 >" umlal gt s r1 r2 r3 r4" C0821493 >" umull gt r1 r2 r3 r4" C0921493 >" umull gt s r1 r2 r3 r4" \ DSP C1C2A0D0 >" ldr gt d r10 [ r2 ]" \ ARM5E C1C2A0DF >" ldr gt d r10 [ r2 0F # ]" C1C2AFD0 >" ldr gt d r10 [ r2 0F0 # ]" C142A0DF >" ldr gt d r10 [ r2 -F # ]" C142AFD0 >" ldr gt d r10 [ r2 -F0 # ]" C182A0D3 >" ldr gt d r10 [ r2 r3 ]" C182A0DD >" ldr gt d r10 [ r2 r13 ]" C102A0D3 >" ldr gt d r10 [ r2 -r3 ]" C1E2A0DF >" ldr gt d r10 [ r2 0F # ] !" C162A0DF >" ldr gt d r10 [ r2 -F # ] !" C1A2A0D3 >" ldr gt d r10 [ r2 r3 ] !" C122A0D3 >" ldr gt d r10 [ r2 -r3 ] !" C0C2A0DF >" ldr gt d r10 [ r2 ] 0F #" C042A0DF >" ldr gt d r10 [ r2 ] -F #" C082A0D3 >" ldr gt d r10 [ r2 ] r3" C002A0D3 >" ldr gt d r10 [ r2 ] -r3" C1C2A0F0 >" str gt d r10 [ r2 ]" \ ARM5E C1C2A0FF >" str gt d r10 [ r2 0F # ]" C1C2AFF0 >" str gt d r10 [ r2 0F0 # ]" C142A0FF >" str gt d r10 [ r2 -F # ]" C142AFF0 >" str gt d r10 [ r2 -F0 # ]" C182A0F3 >" str gt d r10 [ r2 r3 ]" C182A0FD >" str gt d r10 [ r2 r13 ]" C102A0F3 >" str gt d r10 [ r2 -r3 ]" C1E2A0FF >" str gt d r10 [ r2 0F # ] !" C162A0FF >" str gt d r10 [ r2 -F # ] !" C1A2A0F3 >" str gt d r10 [ r2 r3 ] !" C122A0F3 >" str gt d r10 [ r2 -r3 ] !" C0C2A0FF >" str gt d r10 [ r2 ] 0F #" C042A0FF >" str gt d r10 [ r2 ] -F #" C082A0F3 >" str gt d r10 [ r2 ] r3" C002A0F3 >" str gt d r10 [ r2 ] -r3" CC443125 >" mcrr gt p1 2 # r3 r4 c5" \ ARM5E CC49867A >" mcrr gt p6 7 # r8 r9 c10" CC543125 >" mrrc gt p1 2 # r3 r4 c5" \ ARM5E CC59867A >" mrrc gt p6 7 # r8 r9 c10" FC443125 >" mcrr2 p1 2 # r3 r4 c5" \ ARM6 FC49867A >" mcrr2 p6 7 # r8 r9 c10" FC543125 >" mrrc2 p1 2 # r3 r4 c5" \ ARM6 FC59867A >" mrrc2 p6 7 # r8 r9 c10" C1031052 >" qadd gt r1 r2 r3" \ ARM5E C10CA05B >" qadd gt r10 r11 r12" C1231052 >" qsub gt r1 r2 r3" \ ARM5E C12CA05B >" qsub gt r10 r11 r12" C1431052 >" qdadd gt r1 r2 r3" \ ARM5E C14CA05B >" qdadd gt r10 r11 r12" C1631052 >" qdsub gt r1 r2 r3" \ ARM5E C16CA05B >" qdsub gt r10 r11 r12" C1014382 >" smlabb gt r1 r2 r3 r4" \ ARM5E C10ADC8B >" smlabb gt r10 r11 r12 r13" C10143A2 >" smlatb gt r1 r2 r3 r4" \ ARM5E C10ADCAB >" smlatb gt r10 r11 r12 r13" C10143C2 >" smlabt gt r1 r2 r3 r4" \ ARM5E C10ADCCB >" smlabt gt r10 r11 r12 r13" C10143E2 >" smlatt gt r1 r2 r3 r4" \ ARM5E C10ADCEB >" smlatt gt r10 r11 r12 r13" C1214382 >" smlawb gt r1 r2 r3 r4" \ ARM5E C12ADC8B >" smlawb gt r10 r11 r12 r13" C12143C2 >" smlawt gt r1 r2 r3 r4" \ ARM5E C12ADCCB >" smlawt gt r10 r11 r12 r13" C1421483 >" smlalbb gt r1 r2 r3 r4" \ ARM5E C14BAD8C >" smlalbb gt r10 r11 r12 r13" C14214A3 >" smlaltb gt r1 r2 r3 r4" \ ARM5E C14BADAC >" smlaltb gt r10 r11 r12 r13" C14214C3 >" smlalbt gt r1 r2 r3 r4" \ ARM5E C14BADCC >" smlalbt gt r10 r11 r12 r13" C14214E3 >" smlaltt gt r1 r2 r3 r4" \ ARM5E C14BADEC >" smlaltt gt r10 r11 r12 r13" C1610382 >" smulbb gt r1 r2 r3" \ ARM5E C16A0C8B >" smulbb gt r10 r11 r12" C16103A2 >" smultb gt r1 r2 r3" \ ARM5E C16A0CAB >" smultb gt r10 r11 r12" C16103C2 >" smulbt gt r1 r2 r3" \ ARM5E C16A0CCB >" smulbt gt r10 r11 r12" C16103E2 >" smultt gt r1 r2 r3" \ ARM5E C16A0CEB >" smultt gt r10 r11 r12" C12103A2 >" smulwb gt r1 r2 r3" \ ARM5E C12A0CAB >" smulwb gt r10 r11 r12" C12103E2 >" smulwt gt r1 r2 r3" \ ARM5E C12A0CEB >" smulwt gt r10 r11 r12" F5D2F000 >" pld [ r2 ]" \ ARM5E F5DCF000 >" pld [ r12 ]" F5D2F004 >" pld [ r2 4 # ]" F5D2FFFF >" pld [ r2 0FFF # ]" F552F004 >" pld [ r2 -4 # ]" F7D2F003 >" pld [ r2 r3 ]" F7D2F00D >" pld [ r2 r13 ]" F752F003 >" pld [ r2 -r3 ]" F7D2F083 >" pld [ r2 r3 lsl 1 # ]" F7D2FF83 >" pld [ r2 r3 lsl 1F # ]" F7D2F0A3 >" pld [ r2 r3 lsr 1 # ]" F7D2F023 >" pld [ r2 r3 lsr 20 # ]" F7D2F0C3 >" pld [ r2 r3 asr 1 # ]" F7D2F0E3 >" pld [ r2 r3 ror 1 # ]" F7D2F063 >" pld [ r2 r3 rrx ]" F752F083 >" pld [ r2 -r3 lsl 1 # ]" \ ARM6 F1020000 >" cps 0 #" \ ARM6 F102001F >" cps 1F #" F1080100 >" cpsie a" F1080180 >" cpsie ia" F10801C0 >" cpsie fia" F1080040 >" cpsie f" F10A0100 >" cpsie a 0 #" F10A011F >" cpsie a 1F #" F10C0100 >" cpsid a" F1010000 >" setend le" \ ARM6 F1010200 >" setend be" F8110A00 >" rfe da r1" \ ARM6 F8910A00 >" rfe ia r1" F9110A00 >" rfe db r1" F9910A00 >" rfe ib r1" F81B0A00 >" rfe da r11" F8310A00 >" rfe da r1 !" F84D0A00 >" srs da 0 #" \ ARM6 F8CD0A00 >" srs ia 0 #" F94D0A00 >" srs db 0 #" F9CD0A00 >" srs ib 0 #" F86D0A00 >" srs da 0 # !" C1921F9F >" ldrex gt r1 [ r2 ]" \ ARM6 C19CBF9F >" ldrex gt r11 [ r12 ]" C1831F92 >" strex gt r1 r2 [ r3 ]" \ ARM6 C18DBF9C >" strex gt r11 r12 [ r13 ]" C0421493 >" umaal gt r1 r2 r3 r4" \ ARM6 C04CBE9D >" umaal gt r11 r12 r13 lr" C6121F13 >" sadd16 gt r1 r2 r3" \ ARM6 C6121F33 >" saddsubx gt r1 r2 r3" C6121F53 >" ssubaddx gt r1 r2 r3" C6121F73 >" ssub16 gt r1 r2 r3" C6121F93 >" sadd8 gt r1 r2 r3" C6121FF3 >" ssub8 gt r1 r2 r3" C6221F13 >" qadd16 gt r1 r2 r3" C6221F33 >" qaddsubx gt r1 r2 r3" C6221F53 >" qsubaddx gt r1 r2 r3" C6221F73 >" qsub16 gt r1 r2 r3" C6221F93 >" qadd8 gt r1 r2 r3" C6221FF3 >" qsub8 gt r1 r2 r3" C6321F13 >" shadd16 gt r1 r2 r3" C6321F33 >" shaddsubx gt r1 r2 r3" C6321F53 >" shsubaddx gt r1 r2 r3" C6321F73 >" shsub16 gt r1 r2 r3" C6321F93 >" shadd8 gt r1 r2 r3" C6321FF3 >" shsub8 gt r1 r2 r3" C6521F13 >" uadd16 gt r1 r2 r3" C6521F33 >" uaddsubx gt r1 r2 r3" C6521F53 >" usubaddx gt r1 r2 r3" C6521F73 >" usub16 gt r1 r2 r3" C6521F93 >" uadd8 gt r1 r2 r3" C6521FF3 >" usub8 gt r1 r2 r3" C6621F13 >" uqadd16 gt r1 r2 r3" C6621F33 >" uqaddsubx gt r1 r2 r3" C6621F53 >" uqsubaddx gt r1 r2 r3" C6621F73 >" uqsub16 gt r1 r2 r3" C6621F93 >" uqadd8 gt r1 r2 r3" C6621FF3 >" uqsub8 gt r1 r2 r3" C6721F13 >" uhadd16 gt r1 r2 r3" C6721F33 >" uhaddsubx gt r1 r2 r3" C6721F53 >" uhsubaddx gt r1 r2 r3" C6721F73 >" uhsub16 gt r1 r2 r3" C6721F93 >" uhadd8 gt r1 r2 r3" C6721FF3 >" uhsub8 gt r1 r2 r3" C6821013 >" pkhbt gt r1 r2 r3" \ ARM6 C6821F93 >" pkhbt gt r1 r2 r3 lsl 1F #" C68CB01D >" pkhbt gt r11 r12 r13" C6821053 >" pkhtb gt r1 r2 r3 asr 20 #" C6821FD3 >" pkhtb gt r1 r2 r3 asr 1F #" C6A01012 >" ssat gt r1 0 # r2" \ ARM6 C6A0B01C >" ssat gt r11 0 # r12" C6A01092 >" ssat gt r1 0 # r2 lsl 1 #" C6A01F92 >" ssat gt r1 0 # r2 lsl 1F #" C6BF1F92 >" ssat gt r1 1F # r2 lsl 1F #" C6A010D2 >" ssat gt r1 0 # r2 asr 1 #" C6A01052 >" ssat gt r1 0 # r2 asr 20 #" C6E01012 >" usat gt r1 0 # r2" C6E0B01C >" usat gt r11 0 # r12" C6E01092 >" usat gt r1 0 # r2 lsl 1 #" C6E01F92 >" usat gt r1 0 # r2 lsl 1F #" C6FF1F92 >" usat gt r1 1F # r2 lsl 1F #" C6E010D2 >" usat gt r1 0 # r2 asr 1 #" C6E01052 >" usat gt r1 0 # r2 asr 20 #" C6A01F32 >" ssat16 gt r1 0 # r2" \ ARM6 C6A0BF3C >" ssat16 gt r11 0 # r12" C6AF1F32 >" ssat16 gt r1 0F # r2" C6E01F32 >" usat16 gt r1 0 # r2" C6E0BF3C >" usat16 gt r11 0 # r12" C6EF1F32 >" usat16 gt r1 0F # r2" C6821FB3 >" sel gt r1 r2 r3" \ ARM6 C68CBFBD >" sel gt r11 r12 r13" C6821073 >" sxtab16 gt r1 r2 r3" \ ARM6 C68CB07D >" sxtab16 gt r11 r12 r13" C6821473 >" sxtab16 gt r1 r2 r3 ror 8 #" C6821873 >" sxtab16 gt r1 r2 r3 ror 10 #" C6821C73 >" sxtab16 gt r1 r2 r3 ror 18 #" C6A21073 >" sxtab gt r1 r2 r3" C6B21073 >" sxtah gt r1 r2 r3" C6C21073 >" uxtab16 gt r1 r2 r3" C6E21073 >" uxtab gt r1 r2 r3" C6F21073 >" uxtah gt r1 r2 r3" C68F1072 >" sxtb16 gt r1 r2" \ ARM6 C68FB07C >" sxtb16 gt r11 r12" C68F1472 >" sxtb16 gt r1 r2 ror 8 #" C68F1872 >" sxtb16 gt r1 r2 ror 10 #" C68F1C72 >" sxtb16 gt r1 r2 ror 18 #" C6AF1072 >" sxtb gt r1 r2" C6BF1072 >" sxth gt r1 r2" C6CF1072 >" uxtb16 gt r1 r2" C6EF1072 >" uxtb gt r1 r2" C6FF1072 >" uxth gt r1 r2" C6BF1F32 >" rev gt r1 r2" \ ARM6 C6BFBF3C >" rev gt r11 r12" C6BF1FB2 >" rev16 gt r1 r2" C6FF1FB2 >" revsh gt r1 r2" C701F312 >" smuad gt r1 r2 r3" \ ARM6 C70BFD1C >" smuad gt r11 r12 r13" C701F332 >" smuadx gt r1 r2 r3" C701F352 >" smusd gt r1 r2 r3" C70BFD5C >" smusd gt r11 r12 r13" C701F372 >" smusdx gt r1 r2 r3" C751F312 >" smmul gt r1 r2 r3" C75BFD1C >" smmul gt r11 r12 r13" C751F332 >" smmulr gt r1 r2 r3" C7014312 >" smlad gt r1 r2 r3 r4" C70BED1C >" smlad gt r11 r12 r13 lr" C7014332 >" smladx gt r1 r2 r3 r4" C7014352 >" smlsd gt r1 r2 r3 r4" C70BED5C >" smlsd gt r11 r12 r13 lr" C7014372 >" smlsdx gt r1 r2 r3 r4" C7421413 >" smlald gt r1 r2 r3 r4" C74CBE1D >" smlald gt r11 r12 r13 lr" C7421433 >" smlaldx gt r1 r2 r3 r4" C7421453 >" smlsld gt r1 r2 r3 r4" C74CBE5D >" smlsld gt r11 r12 r13 lr" C7421473 >" smlsldx gt r1 r2 r3 r4" C7514312 >" smmla gt r1 r2 r3 r4" C75BED1C >" smmla gt r11 r12 r13 lr" C7514332 >" smmlar gt r1 r2 r3 r4" C75143D2 >" smmls gt r1 r2 r3 r4" C75BEDDC >" smmls gt r11 r12 r13 lr" C75143F2 >" smmlsr gt r1 r2 r3 r4" C781F312 >" usad8 gt r1 r2 r3" \ ARM6 C78BFD1C >" usad8 gt r11 r12 r13" C7814312 >" usada8 gt r1 r2 r3 r4" C78BED1C >" usada8 gt r11 r12 r13 lr" \ ---------------------------------------------------------------------------- \ Use assembler with some labels... CR .( USE ASSEMBLER ) CR CR 4 HERE 3 AND - ALLOT \ align HERE ALSO ARM-ASSEMBLER HERE CODE-BEGIN HERE CHAR " L= terminator L: scan-loop ldr b r0 [ r1 ] 1 # cmp r0 L# terminator bl ne L# scan-loop ldr r0 L# mask mov pc lr L: mask dcd FF00FF00 # L: 1 ldr r2 L# 0 dcd L# 0 dcd L# 1 [[ 123 . CR ]] ldr r2 L# 1 adr r0 . # ldr r2 L# 0 L: 0 HERE CODE-END PREVIOUS OVER - ARM-DISASM \ Disassembler what we just assembled above \ ---------------------------------------------------------------------------- \ Run consistency test... CR .( CONSISTENCY TEST... ) CR CR TEST \ ---------------------------------------------------------------------------- \ Done .( DONE, press any key... ) KEY DROP CR